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Data Sheet No. PD60310
IRS2168D(S)PbF
ADVANCED PFC + BALLAST CONTROL IC
Features
PFC, ballast control and 600 V half-bridge driver in one IC Critical-conduction mode boost-type PFC Programmable PFC over-current protection Programmable half-bridge over-current protection Programmable preheat frequency Programmable preheat time Programmable ignition ramp Programmable run frequency Closed-loop ignition current regulation RoHs compliant Fixed internal 1.6 s HO and LO deadtime Voltage-controlled oscillator (VCO) End-of-life window comparator pin Internal 65-event current sense up/down fault counter DC bus undervoltage reset Lamp removal/auto-restart shutdown pin Internal bootstrap MOSFET Internal 15.6 V Zener clamp diode on Vcc Micropower startup (250 A) Latch immunity and ESD protection
Description
The IRS2168D is a fully integrated, fully protected 600 V ballast control IC designed to drive all types of fluorescent lamps. The IRS2168D is based on the popular IR2166 control IC with additional improvements to increase ballast performance. The PFC circuitry operates in critical conduction mode and provides high PF, low THD and DC bus regulation. The IRS2168D features include programmable preheat and run frequencies, programmable preheat time, programmable PFC over-current protection, closed-loop half-bridge ignition current regulation, and programmable end-of-life protection. Comprehensive protection features such as protection from failure of a lamp to strike, filament failures, end-of-life protection, DC bus undervoltage reset as well as an automatic restart function, have been included in the design.
System Features
One-chip ballast control solution Wide range PFC for universal input and multi-lamp ballasts Ultra low THD Closed-loop ignition regulation for reliable lamp ignition End-of-Life window comparator with internal OTA Lamp removal/auto-restart function Fault counter for robust noise immunity Brown-out protection and reset Internal bootstrap MOSFET
Packages
16-Lead PDIP IRS2168DPBF
16-Lead SOIC IRS2168DSPbF
Application Diagram (Typical Only)
D BUS
+ Rectified AC Line
R VBUS1 R SUPPLY
C VBUS
R CPH
VBUS HO
R GHS M1 C BLOCK LRES C BOOT D CP1 C SNUB R6 R4 M2 D CP2 R7 R8 CRES
1 R VBUS C PH C BUS + C VCO R FMINR RPH CCOMP R1 R GPFC M3 R2
OC CPH
16
VS
2
15
IRS2168D
VCO
VB
3
FMIN
14
VCC
+
4
COMP
13
COM
CVCC1
CVCC2 R GLS R3 D1 R5 RCS
5
ZX
12
LO
6 7
PFC
11
CS
7 8
10
SD/EOL
9
R OC
C OC
C SD1
C CS
C SD2
D2
D3
C EOL
R9
- Rectified AC Line
* Please note that this datasheet contains advanced information that could change before the product is released to production.
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IRS2168D(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defned positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB VS VHO VLO VPFC IO,MAX ICC VBUS VCPH VCOMP VZX VOC VSD/EOL VCS VVCO ICPH IVCO IFMIN ICOMP IZX IOC ISD/EOL ICS dV/dt PD RJA TJ TS TL
Definition
VB pin high-side floating supply voltage VS pin high-side floating supply offset voltage HO pin high-side floating output voltage LO pin low-side output voltage PFC gate driver output voltage Maximum allowable output current (HO, LO, PFC) due to external power transistor miller effect VCC current (see Note 1) VBUS pin voltage CPH pin voltage COMP pin voltage ZX pin voltage OC pin voltage SD/EOL pin voltage CS pin voltage VCO pin voltage CPH pin current VCO pin current FMIN pin current COMP pin current ZX pin current OC pin current SD/EOL pin current CS pin current Allowable VS pin offset voltage slew rate Package power dissipation @ TA +25 C PD = (TJMAX-TA)/RJA Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (16-Pin DIP) (16-Pin SOIC) (16-Pin DIP) (16-Pin SOIC)
Min.
-0.3 VB - 25 VS - 0.3 -0.3 -500 -25
Max.
625 VB + 0.3 VB + 0.3 VCC + 0.3 500 25
Units
V
mA
-0.3
VCC + 0.3
V
-0.3
6
V
-5
5
mA
-50 ---------55 -55 ---
50 1.8 1.4 70 86 150 150 300
V/ns W C/W
C
Note 1: This IC contains a Zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6 V. This supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section.
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IRS2168D(S)PbF
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol
VB-VS VS VCC ICC ISD/EOL ICS IOC IZX VVCO RFMIN TJ
Definition
High-side floating supply voltage Steady state high-side floating supply offset voltage Supply voltage VCC supply current SD/EOL pin current CS pin current
Min.
VBSUV+ -1 VCCUV+ Note 2
Max.
VCLAMP 600 VCLAMP 10
Units
V
mA -1 1
OC pin current ZX pin current VCO pin voltage FMIN pin programming resistor Junction temperature 0 10 -25 5 300 125 V k C
Note 2: Enough current should be supplied into the VCC pin to keep the internal 15.6 V Zener clamp diode on this pin regulated at its voltage, V .
CLAMP
Electrical Characteristics
VCC = VBS = VBIAS=14 V +/- 0.25 V, CLO = CHO = CPFC = 1000 pF, RFMIN = 42.2 k, RPH = N/C, VCPH = VVCO = 0 V, o VSD/EOL = V COMP = VCS = VOC = VBUS = VZX = 0 V, TA=25 C unless otherwise specified.
Symbol
Definition
VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply undervoltage lockout hysteresis UVLO mode VCC quiescent current VCC quiescent current in fault mode
Min
Typ Max
Units
Test Conditions
Supply Characteristics
VCCUV+ VCCUVVUVHYS IQCCUV IQCCFLT 11.5 9.5 1.5 ----12.5 10.5 2.0 220 0.4 13.5 11.5 3.0 320 --mA ICCRUN Run mode VCC supply current --5.5 7.2 A VCC = 8 V MODE=FAULT MODE = RUN VBUS=4 V CSD/EOL=1 nF PFC off time = 5 s ICC = 10 mA V VCC rising from 0 V VCC falling from 14 V
VCLAMP
VCC Zener clamp voltage
14.6
15.6
16.6
V
Floating Supply Characteristics
IBS VBSUV+ VBSUVILKVS VBS supply current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VS offset supply leakage current --8.0 7.0 --0.9 9.0 8.0 --1.3 10.0 V 9.0 50 A VBS falling from 14 V VB = VS = 600 V mA MODE=PREHEAT VBS rising from 0 V
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IRS2168D(S)PbF
Electrical Characteristics (cont'd)
VCC = VBS = VBIAS=14 V +/- 0.25 V, CLO = CHO = CPFC = 1000 pF, RFMIN = 42.2 k, RPH = N/C, VCPH = VVCO = 0 V, o VSD/EOL = VCOMP = VCS = VOC = VBUS = VZX = 0 V, TA=25 C unless otherwise specified.
Symbol
Definition
Min
Typ
Max Units
Test Conditions
MODE = RUN VVBUS = 3.5 V VCOMP=4.0 V MODE = RUN VVBUS = 4.5 V VCOMP=4.0 V VBUS=3.5 V ICOMP=ICOMPSOURCE-5 A
PFC Error Amplifier Characteristics
ICOMP, SOURCE COMP pin OTA error amplifier output current Sourcing COMP pin OTA error amplifier output current Sinking OTA error amplifier output voltage swing (high state) OTA error amplifier output voltage swing (low state) OTA error amplifier output voltage in fault mode 20 30 40 A ICOMP, SINK -40 -30 -20
VCOMPOH
12.0
12.5
13.0 V
VCOMPOL VCOMPFLT
0.2 ---
0.4 0
0.5 ---
VBUS=5.0 V ICOMP=ICOMPSINK+5 A VBUS=4.0 V
PFC Control Characteristics
VVBUSREG VVBUSOV VVBUSOVVZX VZXHYS VZXclamp tBLANK tWD VBUS internal reference voltage VBUS overvoltage comparator threshold VBUS overvoltage fault reset threshold ZX pin threshold voltage ZX pin comparator hysterisis ZX pin clamp voltage (high state) OC pin current-sensing blank time PFC watch-dog pulse interval 3.9 4.1 4.0 1.8 100 5.5 --150 4.0 4.3 4.15 2.0 300 6.5 300 400 4.1 4.5 4.3 2.2 500 7.5 --500 mV V ns s IZX = 1 mA VBUS=4.0 V VCOMP=4.0 V ZX = 0, VCOMP = 4.0 V V VCOMP = 4.0 V
PFC Protection Circuitry Characteristics
VVBUSUVVOCTH+ VBUS pin undervoltage reset threshold OC pin over-current sense threshold 2.7 1.1 3.0 1.2 3.3 V 1.3 VBUS=VCOMP=4.0 V
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IRS2168D(S)PbF
Electrical Characteristics (cont'd)
VCC = VBS = VBIAS=14 V +/- 0.25 V, CLO = CHO = CPFC = 1000 pF, RFMIN = 42.2 k, RPH = N/C, VCPH = VVCO = 0 V, o VSD/EOL = VCOMP = VCS = VOC = VBUS = VZX = 0 V, TA=25 C unless otherwise specified.
Symbol
Definition
Min
Typ
Max
Units Test Conditions
Ballast Control Oscillator Characteristics fOSC, RUN fOSC, PH D td, LO td, HO
VFMIN Half-bridge oscillator run frequency Half-bridge oscillator preheat frequency Oscillator duty cycle LO output deadtime HO output deadtime FMIN pin voltage 42.5 81 --1.1 1.1 1.9 44.5 85 50 1.6 1.6 2.0 46.5 kHz 89 --2.1 s 2.1 2.1 V VCC = 14.0 V % MODE = RUN RPH = 42.2 k, MODE = PREHEAT
Ballast Control Preheat, Ignition and Run Mode Characteristics
VCPHEOP+ VCPHSOIVVCOPH VVCOIGN IVCOIGN VCPHRUN+ VVCORUN CPH pin end of preheat rising threshold voltage CPH pin start of ignition falling threshold voltage VCO pin preheat mode voltage VCO pin ignition mode voltage VCO pin ignition regulation discharge current CPH pin run mode rising threshold voltage VCO pin run mode voltage 8.8 4.6 ----9.3 4.9 0 (Open Drain) 0.6 9.8 5.2 V ----MODE = PREHEAT MODE = IGNITION, VCS < VCSTH+ mA MODE = IGNITION, VVCO = 1 V, VCS > VCSTH+ MODE = IGNITION V --MODE = RUN
---
---
8.8 ---
9.3 (Open Drain)
9.8
Ballast Control Protection Circuitry Characteristics
VCSTH+ CS pin over-current sense threshold CS pin fault counter number of events SD pin rising non-latched shutdown threshold voltage SD pin falling reset threshold voltage EOL pin internal bias voltage EOL pin rising latched shutdown threshold voltage EOL pin falling latched shutdown threshold voltage 1.1 30 4.7 2.5 1.9 2.85 0.9 ----1.2 65 5.2 3.0 2.0 3.0 1.0 10 -10 1.3 100 5.7 3.5 2.1 3.15 1.1 --A IEOL, SINK VCPHFLT VVCOFLT VFMINFLT EOL pin OTA output sinking current CPH pin fault mode voltage VCO pin fault mode voltage FMIN pin fault mode voltage --0 --V MODE = FAULT --V MODE = RUN MODE = RUN MODE = PREHEAT VEOL = 1.5 V MODE = PREHEAT VEOL = 2.5 V V --MODE = PREHEAT or RUN
nEVENTS
VSDTH+ VSDTHVEOLBIAS VEOLTH+ VEOLTH-
IEOL, SOURCE EOL pin OTA output sourcing current
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IRS2168D(S)PbF
Electrical Characteristics (cont'd)
VCC = VBS = VBIAS=14 V +/- 0.25 V, CLO = CHO = CPFC = 1000 pF, RFMIN = 42.2 k, RPH = N/C, VCPH = VVCO = 0 V, o VSD/EOL = VCOMP = VCS = VOC = VBUS = VZX = 0 V, TA=25 C unless otherwise specified.
Gate Driver Output Characteristics (HO, LO and PFC pins)
VOL VOH tr tf I0+ I0Low-level output voltage High-level output voltage Turn-on rise time Turn-off fall time Source current Sink current ------------COM VCC 120 50 180 260 --V --220 ns 100 --mA ---
Bootstrap FET Characteristics
VB/ON IB/CAP IB/10V VB when the bootstrap FET is on VB source current when FET is on VB source current when FET is on 13.0 40 9 13.4 55 12 ----mA --VB=10 V V CBS=0.1 F
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IRS2168D(S)PbF
Schematic Block Diagram
VCC
13
15.6V IFMIN Bootstrap Control Oscillator Driver and Deadtime Logic HighSide Driver
COM
12
VCC
14
VB
16
HO
VCO 3
Ignition Regulation 2V
15
VS
FMIN 4
IFMIN= 2.0V RRFMIN VCC R PH IGN 65 Event Fault Counter R OUT IN VCC RUN VCC UVLO Fault Logic 3V
LowSide Driver
11
LO
CPH 2
R
Mode Logic
10
1.2V
CS
R
2V
+/-10uA
1V
OC 8
1.2V 200ns Blank Time 5V 1M
9
SD/EOL
VBUS 1
Gain
4.0V
OVP OTA1
4.3V
3V
VCC
Ballast Control PFC Control
7
COMP 5
S VCC S 3V R Q Q VBUS Under-Voltage Reset S R1 R2 Q Q R Q Q 400us Watchdog Timer
PFC
ZX 6
2V 6.5V
Please Note: All values shown in block diagram are typical values only.
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IRS2168D(S)PbF
State Diagram
Power Turned On
UVLO Mode
1 /2-Bridge Off IQCCUV 250 A CPH = 0 V VCO = 0 V PFC Off
VCC < 10.5V (VCCUV-) (VCC Fault or Power Down)
SD/EOL > 5.0 V (VSDTH+) (Lamp Removal) or VCC < 10.5 V (VCCUV-) (Power Turned Off)
SD/EOL > 5.0 V (VSDTH+) (Lamp Fault or Lamp Removal)
VCC > 12.5 V (VCCUV+) and SD/EOL < 3.0 V (VSDTH-)
FAULT Mode
Fault Latch Set 1 /2-Bridge Off IQCCFLT 400 A CPH = 0 V VCC = 15.6V VCO = 0 V PFC Off
PREHEAT Mode
/2-Bridge oscillating @ fPH VCO = 0 V RPH // RFMIN CPH charging through RCPH PFC Enabled (High Gain) CS Fault Counter Enabled CPH > 9.3 V (VCPHEOP+) (End of PREHEAT Mode) CPH discharged to CPHSOICPH < 4.9 V (VCPHSOI-) (Start of IGNITION Mode)
1
CS > 1. 2V (VCSTH+) for 65 events (nEVENTS)
CS<1.2 V (VCSTH+) CS Regulation VCO discharged slightly with 0.6 mA current sink (IVCOIGN) CS>1.2 V (VCSTH-) CS > 1.2 V (VCSTH+) for 65 events (nEVENTS) or SD/EOL < 1.0 V (VEOLTH-) or SD/EOL > 3.0 V (VEOLTH+)
IGNITION Mode
CPH charging through RCPH VCO ramping up through RPH fPH ramps to fRUN PFC = High Gain Mode CS Fault Counter Disabled Ignition Regulation Enabled CPH > 9.3 V (VCPHRUN) (End of IGNITION Mode)
RUN Mode
VCO = 2 V 1/2-Bridge Oscillating @fRUN EOL Thresholds Enabled PFC = Low Gain Mode VBUS UV Threshold Enabled CS Fault Counter Enabled Ignition Regulation Disabled VBUS < 3.0 V (VBUSUV-)
Discharge VCC to UVLO
All values are typical. Please refer to application diagram on page 1.
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IRS2168D(S)PbF
Lead Assignments & Definitions
VBUS HO
1
CPH
16
VS
Pin # Symbol
1 VBUS CPH VCO FMIN COMP ZX PFC OC SD/EOL CS LO COM VCC VB VS HO 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Description
DC bus sensing input Preheat timing input Voltage controlled oscillator/ignition ramp input Oscillator minimum frequency setting PFC error amplifier compensation PFC zero-crossing detection PFC gate driver output PFC current sensing input Shutdown/end of life sensing input Half-Bridge current sensing input Low-side gate driver output IC power & signal ground Logic & low-side gate driver supply High-side gate driver floating supply High voltage floating return High-side gate driver output
2
15
3
FMIN
IRS2168D
VCO
VB
14
VCC
4
COMP
13
COM
5
ZX
12
LO
7 6
PFC
11
CS
7
OC
10
SD/EOL
8
9
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IRS2168D(S)PbF
Timing Diagrams Ballast Section
VCC
15.6V UVLO+ UVLO-
CPH
(2/3)*VCC (1/3)*VCC
2V
VCO
tRAMP=RPH*CVCO
frun (RFMIN)
FREQ
f ph (RFMIN//RPH)
SD
HO, LO
CS
1.25V
FAULT
SD > 5V
UVLO
PH
IGN
PH
IGN
RUN
UVLO
HO
HO
HO
LO
LO
1.25V
LO
CS
CS
CS
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IRS2168D(S)PbF
I. Ballast Section Functional Description Undervoltage Lockout Mode (UVLO)
The undervoltage lockout mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold of the IC. To identify the different modes of the IC, refer to the State Diagram shown on page 3 of this document. The IRS2168D undervoltage lockout is designed to maintain an ultra low supply current of 250 A (IQCCUV), and to guarantee the IC is fully functional before the high- and low-side output drivers are activated. Figure 1 shows an efficient supply voltage using the micro-power start-up current of the IRS2168D together with a snubber charge pump from the half-bridge output (RVCC, CVCC1, CVCC2, CSNUB, DCP1 and DCP2).
VRECT (+) VBUS (+) RVCC HO 16 VS 15
BSFET BSFET CONTROL
VC1
CVCC DISCHARGE VUVLO+
VHYST INTERNAL VCC ZENER CLAMP VOLTAGE
VUVLO-
DISCHARGE TIME
CHARGE PUMP OUTPUT RVCC & CVCC1,2 TIME CONSTANT
t
Figure 2: VCC supply voltage
RHO MHS To Load
14 13
VB VCC COM
CBS R2 C VCC1 RLO MLS R3 CCS RCS C VCC2 R1 DCP2
C SNUB
12 LO 11 CS 10 IRS2168D IC COM VBUS(-) Load Return DCP1
Figure 1: Start-up and supply circuitry
The VCC capacitors (CVCC1 and CVCC2) are charged by the current through supply resistor (RVCC) minus the start-up current drawn by the IC. This resistor is chosen to set the desired AC line input voltage turn-on threshold for the ballast. When the voltage at VCC exceeds the IC start-up threshold (VCCUV+) and the SD pin is below 3.0 V (VSDTH-), the IC turns on and LO begins to oscillate. The capacitors at VCC begin to discharge due to the increase in IC operating current (Fig. 2). The high-side supply voltage, VB-VS, begins to increase as capacitor CBS is charged through the internal bootstrap MOSFET during the LO ontime of each LO switching cycle. When the VB-VS voltage exceeds the high-side start-up threshold (VBSUV+), HO then begins to oscillate. This may take several cycles of LO to charge VB-VS above VBSUV+ due to RDSon of the internal bootstrap MOSFET.
When LO and HO are both oscillating, the external MOSFETs (MHS and MLS) are turned on and off with a 50% duty cycle and a non-overlapping deadtime of 1.6 s (td). The half-bridge output (pin VS) begins to switch between the DC bus voltage and COM. During the deadtime between the turn-off of LO and the turn-on of HO, the half-bridge output voltage transitions from COM to the DC bus voltage at a dV/dt rate determined by the snubber capacitor (CSNUB). As the snubber capacitor charges, current will flow through the charge pump diode (DCP2) to VCC. After several switching cycles of the halfbridge output, the charge pump and the internal 15.6 V Zener clamp of the IC take over as the supply voltage. Capacitor CVCC2 supplies the IC current during the VCC discharge time and should be large enough such that VCC does not decrease below UVLO- before the charge pump takes over. Capacitor CVCC1 is required for noise filtering and must be placed as close as possible and directly between VCC and COM, and should not be lower than 0.1 F Resistors R1 and R2 are recommended for limiting high currents that can flow to VCC from the charge pump during hard-switching of the half-bridge or during lamp ignition. The internal bootstrap MOSFET and supply capacitor (CBS) comprise the supply voltage for the high side driver circuitry. During UVLO mode, the high- and low-side driver outputs HO and LO are both low, the internal oscillator is disabled, and pin CPH is connected internally to COM for resetting the preheat time.
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IRS2168D(S)PbF
Preheat Mode (PH)
The IRS2168D enters preheat mode when VCC exceeds the UVLO positive-going threshold (VCCUV+). The internal MOSFET that connects pin CPH to COM is turned off and an external resistor (Fig. 3) begins to charge the external preheat timing capacitor (CPH). LO and HO begin to oscillate at a higher soft-start frequency and ramp down quickly to the preheat frequency. The VCO pin is connected to COM through an internal off and resistor RPH is disconnected from COM. The equivalent resistance at the FMIN pin increases from the parallel combination (RPH//RFMIN) to RFMIN at a rate programmed by the external capacitor at pin VCO (CVCO) and resistor RPH. This causes the operating frequency to ramp down smoothly from the preheat frequency through the ignition frequency to the final run frequency. During this ignition ramp, the frequency sweeps through the resonance frequency of the lamp output stage to ignite the lamp.
VCPH
VBUS (+) VCC
2/3*VCC
R CPH C PH
CPH
3
HO MODE HalfBridge Driver
16
MHS
1/3*VCC
HalfBridge Output ILOAD
C VCO
VCO
4
M1
VS
15
tPH = RCPH * CPH
R PH
t VVCO
2V tRAMP = RPH * CVCO
FMIN
5 R FMIN
OSC.
11
LO
MLS
CS R 3
10
t
IRS2168D
C CS 12
PREHEAT
R CS
IGNITION
RUN
COM
Load Return VBUS (-)
Figure 4: CPH and VCO timing diagram
VBUS (+) VCC
Figure 3: Preheat circuitry
R CPH
MOSFET M1 so the preheat frequency is determined by the equivalent resistance at the FMIN pin formed by the parallel combination of resistors RFMIN and RPH. The frequency remains at the preheat frequency until the voltage on pin CPH exceeds approvixmately 2/3*VCC (VCPHEOP+) and the IC enters Ignition Mode. During preheat mode, the over-current protection on pin CS and the 65-cycle (nEVENTS) consecutive over-current fault counter are both enabled. The PFC circuit is working in high-gain mode (see PFC section) and keeps the DC bus voltage regulated at a constant level.
VBUS (-)
C PH
CPH
3
HO MODE HalfBridge Driver
16
MHS
C VCO
VCO
4
M1
VS
15
HalfBridge Output ILOAD
R PH
FMIN
5 R FMIN
OSC.
11
LO
MLS
IGN. REG.
CS R 3 + 12 10 1.25V C CS
IRS2168D
COM
R CS
Load Return
Ignition Mode (IGN)
The IRS2168D ignition mode is defined by the second time CPH charges from 1/3*VCC (VCPHSOI-) to 2/3*VCC (VCPHRUN+). When the voltage on pin CPH exceeds 2/3*VCC (VCPHRUN+) for the first time, pin CPH is discharged quickly through an internal MOSFET down to 1/3*VCC (VCPHSOI-) (see Figs. 4 and 5). The internal MOSFET turns off and the voltage on pin CPH begins to increase again. The internal MOSFET M1 at pin VCO turn
Figure 5: Ignition circuitry
The over-current threshold on pin CS will protect the ballast against a non-strike or open-filament lamp fault condition. The voltage on pin CS is defined by the lower half-bridge MOSFET current flowing through the external current sensing resistor RCS. This resistor programs the maximum peak ignition current (and therefore peak
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IRS2168D(S)PbF
ignition voltage) of the ballast output stage. Should this voltage exceed the internal threshold of 1.2 V (VCSTH+), the ignition regulation circuit controls the voltage on the VCO pin to increase the frequency slightly (see Fig. 6). This cycle-by-cycle feedback from the CS pin to the VCO pin will adjust the frequency each cycle to limit the amplitude of the current for the entire duration of ignition mode.
VOUT
HO LO VS
VCPH
VCS
1.25V
t
tPH tRAMP
tIGN
t
Figure 7: Ballast output voltage and CPH pin during preheat and ignition with deactivated lamp, time span 100ms
VVCO
2V
VOUT
t
Figure 6: Ignition regulation timing diagram
When CPH exceeds 2/3*VCC (VCPHRUN+) for the second time, the IC enters run mode and the fault counter becomes enabled. The ignition regulation disabled in run mode but the IC will enter fault mode after 65 (nEVENTS) consecutive over-current faults and gate driver outputs HO, LO and PFC will be latched low. The output voltage of the ballast will increase during the ignition ramp tRAMP because the frequency ramp down from the preheat frequency to the ignition frequency and will be constant during ignition because the ignition regulation circuit will regulate the amplitude of the current for the entire duration of the ignition time tIGN (Figs. 7 and 8). During ignition mode, the PFC circuit is working in highgain mode and keeps the DC bus voltage regulated at a constant level. The high-gain mode is necessary to prevent the DC bus from decreasing during lamp ignition or ignition regulation. Also during ignition mode, the SD/EOL fault is disabled.
VCPH
tIGN tRAMP
Figure 8: Ballast output voltage and CPH pin during preheat and ignition with deactivated lamp, time span 50ms
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IRS2168D(S)PbF
Run Mode (RUN)
Once VCC has exceeded 2/3*VCC (VCPHRUN+) for the second time, the IC enters run mode. CPH continues to charge up to VCC. The operating frequency is at the minimum frequency (after the ignition ramp) and is programmed by the external resistor (RFMIN) at the FMIN pin. Should hard-switching occur at the half-bridge at any time (open-filament, lamp removal, etc.), the voltage across the current sensing resistor (RCS) will exceed the internal threshold of 1.2 V (VCSTH+) and the fault counter will begin counting (see Fig. 5). Should the number of consecutive over-current faults exceed 65 (nEVENTS), the IC will enter fault mode and the HO, LO and PFC gate driver outputs will be latched low. During run mode, the end-of-life (EOL) window comparator and the DC bus undervoltage reset are both enabled.
SD/EOL and CS Fault Mode
Should the voltage at the SD/EOL pin exceed 3.0 V (VEOLTH+) or decrease below 1.0 V (VEOLTH-) during run mode, an end-of-life (EOL) fault condition has occurred and the IC enters fault mode. LO, HO and PFC gate driver outputs are all latched off in the `low' state. CPH is discharged to COM for resetting the preheat time and VCO is discharged to COM for resetting the frequency. To exit fault mode, VCC can be decreased below VCCUV(ballast power off) or the SD pin can be increased above 5.0 V (VSDTH+) (lamp removal). Either of these will force the IC to enter UVLO mode (see State Diagram, page 3). Once VCC is above VCCUV+ (ballast power on) and SD is pulled above 5.0 V (VSDTH+) and back below 3.0 V (VSDTH-) (lamp re-insertion), the IC will enter preheat mode and begin oscillating again. The current sense function will force the IC to enter fault mode only after the voltage at the CS pin has been greater than 1.2 V (VCSTH+) for 65 (nEVENTS) consecutive cycles of LO. The voltage at the CS pin is AND-ed with LO (see Fig. 9) so it will work with pulses that occur during the LO on-time or DC. If the over-current faults are not consecutive, then the internal fault counter will count back down each cycle when there is no fault. Should an over-current fault occur only for a few cycles and then not occur again, the counter will eventually reset to zero. The over-current fault counter is enabled during preheat and run modes and disabled during ignition mode.
50 Cycles LO
DC Bus Undervoltage Reset
Should the DC bus decrease too low during a brown-out line condition or over-load condition, the resonant output stage to the lamp can shift near or below resonance. This can produce hard switching at the half- bridge that can damage the half-bridge switches, or, the DC bus can decrease too far and the lamp can extinguish. To protect against this, the VBUS pin includes a 3.0 V undervoltage reset threshold VBUSUV-. When the IC is in run mode and the voltage at the VBUS pin decreases below 3.0 V (VBUSUV), VCC will be discharged through an internal MOSFET down to the VCCUV- threshold and all gate driver outputs will be latched low. For proper ballast design, the designer should set the over-current limit of the PFC section such that the DC bus does not drop until the AC line input voltage falls below the minimum rated input voltage of the ballast (see PFC section). When the PFC over-current limit is correctly set, the DC bus voltage will start to decrease when over-current is reached during low-line conditions. The voltage measured at the VBUS pin will decrease below the internal 3.0 V threshold VBUSUVand the ballast will turn off cleanly. The pull-up resistor to VCC (RVCC) will then turn the ballast on again when the AC input line voltage increases high enough again where VCC exceeds VCCUV+. RVCC should be set to turn the ballast on at the minimum specified ballast input voltage and the PFC over-current should be set somewhere below this level. This hysteresis will result in clean turn-on and turnoff of the ballast.
CS
1.25V
Run or Preheat Mode
Fault Mode
Figure 9: Fault counter timing diagram
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IRS2168D(S)PbF
II. PFC Section Functional Description
In most electronic ballasts it is necessary to have the circuit act as a pure resistive load to the AC input line voltage. The degree to which the circuit matches a pure resistor is measured by the phase shift between the input voltage and input current and how well the shape of the input current waveform matches the shape of the sinusoidal input voltage. The cosine of the phase angle between the input voltage and input current is defined as the power factor (PF), and how well the shape of the input current waveform matches the shape of the input voltage is determined by the total harmonic distortion (THD). A power factor of 1.0 (maximum) corresponds to zero phase shift and a THD of 0% and represents a pure sinusoidal waveform (no distortion). For this reason it is desirable to have a high PF and a low THD. To achieve this, the IRS2168D includes an active power factor correction (PFC) circuit. The control method implemented in the IRS2168D is for a boost-type converter (Fig. 10) running in criticalconduction mode (CCM). This means that during each switching cycle of the PFC MOSFET, the circuit waits until the inductor current discharges to zero before turning the PFC MOSFET on again. The PFC MOSFET is turned on and off at a much higher frequency (>10 kHz) than the line input frequency (50 to 60 Hz).
LPFC (+) DPFC DC Bus
V, I
t
Figure 11: Sinusoidal line input voltage (solid line), triangular PFC Inductor current and smoothed sinusoidal line input current (dashed line) over one half-cycle of the AC line input voltage
When the line input voltage is low (near the zero crossing), the inductor current will charge up to a small amount and the discharge time will be fast resulting in a high switching frequency. When the input line voltage is high (near the peak), the inductor current will charge up to a higher amount and the discharge time will be longer giving a lower switching frequency. The PFC control circuit of the IRS2168D (Fig. 12) includes five control pins: VBUS, COMP, ZX, PFC and OC. The VBUS pin measures the DC bus voltage via an external resistor voltage divider. The COMP pin programs the on-time of MPFC and the speed of the feedback loop with an external capacitor. The ZX pin detects when the inductor current discharges to zero each switching cycle using a secondary winding from the PFC inductor. The PFC pin is the low-side gate driver output for the external MOSFET, MPFC. The OC pin senses the current flowing through MPFC and performs cycle-by-cycle over-current protection.
LPFC
+ MPFC (-) CBUS
(+)
DFPC
Figure 10: Boost converter circuit
RVBUS1
RZX RVBUS2
When the switch MPFC is turned on, the inductor LPFC is connected between the rectified line input (+) and (-) causing the current in LPFC to charge up linearly. When MPFC is turned off, LPFC is connected between the rectified line input (+) and the DC bus capacitor CBUS (through diode DPFC) and the stored current in LPFC flows into CBUS. MPFC is turned on and off at a high frequency and the voltage on CBUS charges up to a specified voltage. The feedback loop of the IRS2168D regulates this voltage to a fixed value by continuously monitoring the DC bus voltage and adjusting the on-time of MPFC accordingly. For an increasing DC bus the on-time is decreased, and for a decreasing DC bus the on-time is increased. This negative feedback control is performed with a slow loop speed and a low loop gain such that the average inductor current smoothly follows the low-frequency line input voltage for high power factor and low THD. The on-time of MPFC therefore appears to be fixed (with an additional modulation to be discussed later) over several cycles of the line voltage. With a fixed on-time, and an off-time determined by the inductor current discharging to zero, the result is a system where the switching frequency is free-running and constantly changing from a high frequency near the zero crossing of the AC input line voltage, to a lower frequency at the peaks (Fig. 11).
VBUS
ZX
PFC Control
COMP
CBUS PFC OC RPFC MPFC
COM ROC RVBUS CCOMP
(-)
Figure 12: IRS2168D simplified PFC control circuit
The VBUS pin is regulated against a fixed internal 4.0 V reference voltage for regulating the DC bus voltage (Fig. 13). The feedback loop is performed by an operational transconductance amplifier (OTA) that sinks or sources a current to the external capacitor at the COMP pin. The resulting voltage on the COMP pin sets the threshold for the charging of the internal timing capacitor (C1, Figure 13) and therefore programs the on-time of MPFC. During preheat and ignition modes of the ballast section, the gain of the OTA is set to a high level to raise the DC bus level quickly and to minimize the transient on the DC bus that can occur during ignition. During run mode, the gain is then decreased to a lower level necessary for a slower
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IRS2168D(S)PbF
loop speed for achieving high power factor and low THD.
On-time Modulation Circuit
A fixed on-time of MPFC over an entire cycle of the line input voltage produces a peak inductor current which naturally follows the sinusoidal shape of the line input voltage. The smoothed averaged line input current is in phase with the line input voltage for high power factor but the total harmonic distortion (THD), as well as the individual higher harmonics, of the current can still be too high. This is mostly due to cross-over distortion of the line current near the zero-crossings of the line input voltage. To achieve low harmonics that are acceptable to international standard organizations and general market requirements, an additional on-time modulation circuit has been added to the PFC control. This circuit dynamically increases the on-time of MPFC as the line input voltage nears the zero-crossings (Fig. 15). This causes the peak LPFC current, and therefore the smoothed line input current, to increase slightly higher near the zerocrossings of the line input voltage. This reduces the amount of cross-over distortion in the line input current which reduces the THD and higher harmonics to low levels.
Run Mode Signal
Fault Mode Signal
VBUS 1
GAIN 4.0V OTA1 4.3V COMP4 VCC
COMP 5
M1 COMP2 Discharge VCC to UVLOC1 M2
COMP5
RS3 S Q
7
PFC
RQ WATCH DOG TIMER
3.0V
8
1.2V SQ RS4 R1 R2 Q
OC
ZX 6
5.1V 2.0V
COMP3
Figure 13: IRS2168D detailed PFC control circuit
The off-time of MPFC is determined by the time it takes the LPFC current to discharge to zero. The zero current level is detected by a secondary winding on LPFC that is connected to the ZX pin through an external current limiting resistor RZX. A positive-going edge exceeding the internal 2 V threshold (VZXTH+) signals the beginning of the off-time. A negative-going edge on the ZX pin falling below 1.7 V (VZXTH+ - VZXHYS) will occur when the LPFC current discharges to zero which signals the end of the off-time and MPFC is turned on again (Fig. 14). The cycle repeats itself indefinitely until the PFC section is disabled due to a fault detected by the ballast section (Fault Mode), an over-voltage or undervoltage condition on the DC bus, or, the negative transition of ZX pin voltage does not occur. Should the negative edge on the ZX pin not occur, MPFC will remain off until the watch-dog timer forces a turn-on of MPFC for an on-time duration programmed by the voltage on the COMP pin. The watch-dog pulses occur every 400 s (tWD) indefinitely until a correct positive- and negative-going signal is detected on the ZX pin and normal PFC operation is resumed. Should the OC pin exceed the 1.2 V (VOCTH+) over-current threshold during the on-time, the PFC output will turn off. The circuit will then wait for a negative-going transition on the ZX pin or a forced turn-on from the watch-dog timer to turn the PFC output on again.
ILPFC
0
PFC pin
0
near peak region of rectified AC line
near zero-crossing region of rectified AC line
Figure 15: On-time modulation circuit timing diagram
DC Bus Over-voltage Protection
Should over-voltage occur on the DC bus and the VBUS pin exceeds the internal 4.3 V threshold (VBUSOV+), the PFC output is disabled (set to a logic `low'). When the DC bus decreases again and the VBUS pin decreases below the internal 4.15 V threshold (VBUSOV-), a watch-dog pulse is forced on the PFC pin and normal PFC operation is resumed.
ILPFC ...
DC Bus Undervoltage Reset
PFC ...
ZX
...
1.2V
OC
...
Figure 14: Inductor current, PFC pin, ZX pin and OC pin timing diagram
When the input line voltage decreases, the on-time of MPFC increases to keep the DC bus constant. The ontime will continue to increase as the line voltage continues to decrease until the OC pin exceeds the internal 1.2 V over-current threshold (VOCTH+). At this time, the on-time can no longer increase and the PFC can no longer supply enough current to keep the DC bus fixed for the given load power. This will cause the DC bus to begin to decrease. The decreasing DC bus will cause the VBUS pin to decrease below the internal 3.0 V threshold (VBUSUV-) (Fig. 12).
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IRS2168D(S)PbF
When this occurs, VCC is discharged internally to UVLO. The IRS2168D enters UVLO mode and both the PFC and ballast sections are disabled. The start-up supply resistor to VCC, together with the micro-power start-up current, should be set such that the ballast turns on at an AC line input voltage above the level at which the DC bus begins to drop. The current-sensing resistor at the OC pin sets the maximum PFC current and therefore sets the maximum on-time of MPFC. This prevents saturation of the PFC inductor and programs the minimum low-line input voltage for the ballast. The micro-power supply resistor to VCC and the current-sensing resistor at the OC pin program the on and off input line voltage thresholds for the ballast. With these thresholds correctly set, the ballast will turn off due to the 3.0 V undervoltage threshold (VBUSUV-) on the VBUS pin, and on again at a higher voltage (hysterisis) due to the supply resistor to VCC.
Step 3: Program Preheat Time and Ignition Time The preheat time is defined by the time it takes for the external capacitor on pin CPH to charge up to VCPHEOP+. An external resistor (RCPH) connected to VCC charges capacitor CPH. The preheat time is therefore given as:
tPH RCPH CPH
or
[s]
(2)
CPH
tPH RCPH
[F]
(3)
The ignition time is defined by the time it takes for the external capacitor on pin CPH to charge up the second time from VCPHSOI- to VCPHRUN. The ignition time is therefore given as:
III. Ballast Design Equations
Note: The results from the following design equations can differ slightly from actual measurements due to IC tolerances, component tolerances, and oscillator over- and under-shoot due to internal comparator response time. Step 1: Program Run Frequency The run frequency is programmed with the timing resistor RFMIN at the FMIN pin. Use graph in Fig. 16 (RFMIN vs. Frequency) to select RFMIN value for desired run frequency.
140 120 100 Frequency (kHz) 80 60 40 20 0 10 20 30 RFMIN (kW) 40 50
t IGN 0.4 t PH
Step 4: Program Ignition Ramp Time
[s]
(4)
The ignition ramp time is defined by the time it takes for the external capacitor on pin VCO to charge up to 2 V. The external timing resistor (RPH) connected to FMIN charges capacitor CVCO. The ignition ramp time is therefore given as:
t RAMP = RPH CVCO
or
[s]
(5)
CVCO
tRAMP RPH
[F]
(6)
Step 5: Program Maximum Ignition Current The maximum ignition current is programmed with the external resistor RCS and an internal threshold of 1.2 V (VCSTH+). This threshold determines the over-current limit of the ballast, which will be reached when the frequency ramps down towards resonance during ignition and the lamp does not ignite. The maximum ignition current is given as:
Figure 16: fOSC vs RFMIN
Step 2: Program Preheat Frequency The preheat frequency is programmed with timing resistors RFMIN and RPH. The timing resistors are connected in parallel for the duration of the preheat time. Use graph in Fig. 14 (RFMIN vs. Frequency) to select REQUIV value for desired preheat frequency. Then RPH is given as:
I IGN
1.2 RCS 1.2 I IGN
[A] (peak)
(7)
or
RCS
[] (8)
RPH =
RFMIN REQUIV RFMIN - REQUIV
[]
(1)
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IRS2168D(S)PbF
IV. PFC Design Equations
Step1: Calculate PFC inductor value:
LPFC =
(8e - 6) (VBUS - VACRMS 2 ) VACRMS 2 2 POUT
[H]
(1)
where,
VBUS VAC RMS
POUT
= = = =
DC bus voltage Nominal rms AC input voltage PFC efficiency (typically 0.95) Ballast output power
Step 2: Calculate peak PFC inductor current:
i PK =
2 2 POUT VAC MIN
[A] (peak)
(2)
where,
VAC MIN
=
Minimum rms AC input voltage
Note: The PFC inductor must not saturate at i PK over the specified ballast operating temperature range. Proper core sizing and air-gapping should be considered in the inductor design.
Step 3: Calculate PFC over-current resistor ROC value:
ROC =
1.2 iPK
[]
(3)
Step 4: Calculate start-up resistor RVCC value:
RVCC =
VAC MIN
+ 10
PK
[]
(4)
IQCCUV
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IRS2168D(S)PbF
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IRS2168D(S)PbF
LOADED TAPE FEED DIRECTION
B
A
H
D F C
NOTE : CONTROLLING DIM ENSION IN M M
E G
CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 15.70 16.30 D 7.40 7.60 E 6.40 6.60 F 10.20 10.40 G 1.50 n/a H 1.50 1.60
16SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.618 0.641 0.291 0.299 0.252 0.260 0.402 0.409 0.059 n/a 0.059 0.062
F
D C E B A
G
H
REEL DIMENSIONS FOR 16SOICN Metric Imperial Code Min Max Min Max A 329.60 330.25 12.976 13.001 B 20.95 21.45 0.824 0.844 C 12.80 13.20 0.503 0.519 D 1.95 2.45 0.767 0.096 E 98.00 102.00 3.858 4.015 F n/a 22.40 n/a 0.881 G 18.50 21.10 0.728 0.830 H 16.40 18.40 0.645 0.724
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IRS2168D(S)PbF
ORDER INFORMATION
16-Lead PDIP IRS2168DPBF 16-Lead SOIC IRS2168DSPbF 16-Lead SOIC Tape & Reel IRS2168DSTRPbF
The SOIC-16 is MSL3 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 Data and specifications subject to change without notice. 1/26/2007
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